Your Browsing History
Meet Your Seller
JTAG HS3 Programming Cable
- Small, complete, all-in-one JTAG programming/debugging solution for Xilinx FPGAs and SoCs
- Plugs directly into standard Xilinx JTAG header. Open drain buffer on pin 14 allows debugging software to reset the processor core of Xilinx's Zynq platform
- Separate Vref drives JTAG signal voltages; Vref can be any voltage between 1.8V and 5V
- High-Speed USB2 port that can drive JTAG bus up to 30Mbit/sec (frequency adjustable by user)
- Compatible with Xilinx ISE 14.1 and newer, Xilinx Vivado 2013.3 and newer
+
+
Overview
Specs
Reviews
Small, complete, all-in-one JTAG programming/debugging solution for Xilinx FPGAs and SoCs
Plugs directly into standard Xilinx JTAG header. Open drain buffer on pin 14 allows debugging software to reset the processor core of Xilinx's Zynq platform
Separate Vref drives JTAG signal voltages; Vref can be any voltage between 1.8V and 5V
High-Speed USB2 port that can drive JTAG bus up to 30Mbit/sec (frequency adjustable by user)
Compatible with Xilinx ISE 14.1 and newer, Xilinx Vivado 2013.3 and newer
Plugs directly into standard Xilinx JTAG header. Open drain buffer on pin 14 allows debugging software to reset the processor core of Xilinx's Zynq platform
Separate Vref drives JTAG signal voltages; Vref can be any voltage between 1.8V and 5V
High-Speed USB2 port that can drive JTAG bus up to 30Mbit/sec (frequency adjustable by user)
Compatible with Xilinx ISE 14.1 and newer, Xilinx Vivado 2013.3 and newer
Warranty & Returns
Warranty, Returns, And Additional Information
Warranty
- Please contact the Seller directly for warranty information. Warranty information may also be found on the Manufacturer's website.
- CONTACT
Return Policies
- This item is covered by CITY BUSINESS LIMITED Return Policy
Manufacturer Contact Info
- For a directory of all our manufacturers, please click below.
- Manufacturers Directory
LOADING...